Cache Simulator

Project Description
The goal of this project was to simulate a single level of cache in software. The simulator was to take a provided input address trace as its input and implement the workings of a cache. Specifically, the simulator kept track oh wich blocks are brought into the cache and which blocks are being evicted. Then at the completion of the trace, the simulator would provide statistics about cache hit ratio, read traffic, write traffic, etc.

Structure of Simulator
The simulator takes an address trace as its input. The trace captures the sequence of accesses that are being made to the cache. For each access, the trace provides the type of access and the memory address that is being accessed. Each line in the trace has the following format: Access_type Hex_Address

Access_type signifies the type of memory operation (read write or invalidate). It is encoded as follows: Access_type = 0 indicates a read, Access_type = 1 indicates a write and Access_type = 2 indicates an invalidate operation.

The following parameters are configurable in the cache simulator:
  • num_sets
  • num_ways(associativity)
  • line_size(in bytes)
  • replacement poicy: supports True LRU and 1-bit LRU
After the last access in the trace has been simulated, the simulator output includes the following statistics:
  • Total number of cache accesses
  • Number of cache reads
  • Number of cache writes
  • Number of invalidates
  • Number of cache hits
  • Number of cache misses
  • Cache hit ratio
  • Cache miss ratio
  • Number of evictions
  • Number of writebacks